Internal signals of integrated circuits are processed in a differential mode for enhancing rejection of noise coming from the supply lines and from the silicon substrate. It is often necessary to provide these circuits with an output stage that converts the differential signal to a single-ended signal to reduce the number of pins and to simplify the printed circuit board (PCB).
Moreover, especially in RF applications, this output stage should match the load impedance for maximizing the power delivered to the load. FIG. 1 depicts a typical architecture of a differential to single-ended converter for RF applications. The circuit includes a differential pair of transistors input with the differential signal to be converted, and a transformer that provides a single-ended version of the input differential signal to a load RL. The block MN is an impedance matching network for maximizing the power delivered to the load RL.
This approach is burdened by the following drawbacks that limit its use:                the integrated transformer occupies a relatively large silicon area;        the level of the single-ended output signal depends on the coupling coefficient k of the primary and secondary windings of the transformer that is relatively small;        the impedance matching network MN includes resonant circuits and it is not possible to ensure a precisely determined output impedance over a relatively wide range of frequencies;        the parasitic capacitances of the integrated transformer are not negligible and cause an asymmetry that reduces the common mode rejection ratio of the converter (CMRR).        
Another common differential to single-ended converter is depicted in FIG. 2. This architecture substantially comprises a differential pair of transistors, input with the differential signal In+, In− to be converted, and a common emitter transistor Q3 with a degeneration resistor Ro. The bias current of the transistor Q3 and the degeneration resistor Ro are determined according to the following equation for matching the load impedance:
                              R          L                =                              R            O                    +                      1                          g              m                                                          (        1        )            wherein gm is the transconductance of the transistor Q3.
A drawback of this converter is that only the signal on a single collector of the differential pair is used, thus the voltage level of the output single-ended signal is halved. Furthermore, the output signal may be corrupted by noise on the supply lines or generated by the bias current generator. Moreover, since the base-emitter impedance of the common emitter node of the differential pair diminishes with the working frequency, the common mode rejection ratio of the differential pair becomes relatively small at high frequency.